Method and apparatus for synchronization of clock domains

ABSTRACT

A method and an apparatus for synchronizing clock domains. A slow clock signal is received. A circuit in a slow clock domain is operated based upon the slow clock signal. A fast clock signal is received. The slow clock signal is synchronized using the fast clock signal. The operation of the circuit is modified from the slow clock domain to the fast clock domain, modifying the operation comprising changing a clock operation frequency during a non-transition period of the slow clock.

FIELD OF THE INVENTION

This invention relates generally to acquisition of physiological data,and, more particularly, to a method and apparatus for performingsynchronization between clock domains.

DESCRIPTION OF THE RELATED ART

The technology explosion in the implantable medical devices industry hasresulted in many new and innovative devices and methods for analyzingand improving the health of a patient. The class of implantable medicaldevices now includes pacemakers, implantable cardioverters,defibrillators, neural stimulators, and drug administering devices,among others. Today's state-of-the-art implantable medical devices arevastly more sophisticated and complex than early ones, capable ofperforming significantly more complex tasks. The therapeutic benefits ofsuch devices have been well proven.

There are many implementations of implantable medical devices thatprovide data acquisition of important physiological data from a humanbody. Many implantable medical devices are used for cardiac monitoringand therapy. Often these devices comprise sensors that are placed inblood vessels and/or chambers of the heart. Often these devices areoperatively coupled with implantable monitors and therapy deliverydevices. For example, such cardiac systems include implantable heartmonitors and therapy delivery devices, such as pacemakers, cardioverter,defibrillators, heart pumps, cardiomyostimulators, ischemia treatmentdevices, drug delivery devices, and other heart therapy devices. Most ofthese cardiac systems include electrodes for sensing and gain amplifiersfor recording and/or driving sense event signals from the inter-cardiacor remote electrogram (EGM).

As the functional sophistication and complexity of implantable medicaldevice systems have increased over the years, it has become increasinglyuseful to include a system for operation in a multi-mode fashion.Multi-mode operation may be used to conserve battery resources in theimplantable medical device. Many body-implantable medical devices mayreceive operational power from an internal power source, such as abattery. The battery may serve a variety of functions, including, butnot limited to, supplying power to electronic components of the deviceand charging capacitors that may discharge through electric leads intothe heart to regulate heart rhythms. Conserving battery power isimportant, since replacing a battery from an implantable medical devicecan be invasive. Therefore, much effort has been devoted to increaseconservation of battery resources.

Use of multi-mode operation may lead to more efficient use of batterypower, however, switching between the multi-mode operations may causemalfunctions in the implantable medical device. Often, when switchingoperation-mode to another, certain errors, ringing, false signal rises,etc., may occur. Such errors can cause malfunction of a circuit, makingthe overall implantable medical system unpredictable at times. Errorsoccurring in implantable medical devices can cause harm to the health ofa patient.

The present invention is directed to overcoming, or at least reducingthe effects of, one or more of the problems set forth above.

SUMMARY OF THE INVENTION

In one aspect of the present invention, a method is provided forperforming synchronization between clock domains. A slow clock signal isreceived. A circuit in a slow clock domain is operated based upon theslow clock signal. A fast clock signal is received. The slow clocksignal is synchronized using the fast clock signal. The operation of thecircuit is modified from the slow clock domain to the fast clock domain,modifying the operation comprising changing a clock operation frequencyduring a non-transition period of the slow clock.

In another aspect of the present invention, an apparatus is providedperforming synchronization between clock domains. The apparatus of thepresent invention comprises: a processor; a control logic operativelycoupled to the processor, the control logic to generate at least onecontrol signal in response to a command from the processor; a dataacquisition controller operatively coupled with the control logic, thedata acquisition controller to acquire physiological data in response toan assertion of at least one control signal from the control logic; anda clock controller operatively coupled with the control logic, the clockcontroller to modify a operation clock from a slow clock domain to afast clock domain by synchronizing the slow clock domain to the fastclock domain, the clock controller being capable of performing aoperating clock transition during a non-transition period of the slowclock.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention may be understood by reference to the followingdescription taken in conjunction with the accompanying drawings, inwhich like reference numerals identify like elements, and in which:

FIG. 1 is a simplified diagram of an implementation of an implantablemedical device in accordance with one illustrative embodiment of thepresent invention;

FIG. 2 illustrates a simplified block diagram representation of animplantable medical device system in accordance with one illustrativeembodiment of the present invention;

FIG. 3 illustrates a more detailed block diagram representation of anaccess device of FIG. 2, in accordance with one illustrative embodimentof the present invention;

FIG. 4 illustrates a more detailed block diagram representation of animplantable medical device of FIG. 2, in accordance with oneillustrative embodiment of the present invention;

FIG. 5 illustrates a time-line diagram of a clock switching function inaccordance with one embodiment of the present invention;

FIG. 6 illustrates a block diagram representation of the operation of aclock controller of FIG. 4, in accordance with one illustrativeembodiment of the present invention;

FIG. 7 illustrates a block diagram representation of the clockcontroller of FIG. 4, in accordance with one illustrative embodiment ofthe present invention;

FIGS. 8 a and 8 b illustrate a timing diagram relating tosynchronization of clock domains, in accordance with one illustrativeembodiment of the present invention;

FIG. 9 illustrates a block diagram representation of performing aclock-mode switching, in accordance with one illustrative embodiment ofthe present invention;

FIG. 10 illustrates a flowchart depiction of the method in accordancewith illustrative one embodiment of the present invention;

FIG. 11 illustrates a simplified depiction of a state machine inaccordance with one illustrative embodiment of the present invention;

FIG. 12 illustrates a timing diagram relating to the state machine ofFIG. 11, in accordance with one illustrative embodiment of the presentinvention; and

Appendix A provides an example of implementing a hardware descriptivelanguage to provide the synchronization of clock domains, in accordancewith one embodiment of the present invention.

While the invention is susceptible to various modifications andalternative forms, specific embodiments thereof have been shown by wayof example in the drawings and are herein described in detail. It shouldbe understood, however, that the description herein of specificembodiments is not intended to limit the invention to the particularforms disclosed, but on the contrary, the intention is to cover allmodifications, equivalents, and alternatives falling within the spiritand scope of the invention as defined by the appended claims.

DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS

Illustrative embodiments of the invention are described below. In theinterest of clarity, not all features of an actual implementation aredescribed in this specification. It will of course be appreciated thatin the development of any such actual embodiment, numerousimplementation-specific decisions must be made to achieve thedevelopers' specific goals, such as compliance with system-related andbusiness-related constraints, which will vary from one implementation toanother. Moreover, it will be appreciated that such a development effortmight be complex and time-consuming, but would nevertheless be a routineundertaking for those of ordinary skill in the art having the benefit ofthis disclosure.

There are many discrete processes involving collecting, storing, andpresenting physiological trends of a patient, as well as in deliveringtherapies (e.g., a cardiac therapy). A battery located within animplantable medical device provides the power necessary for performingsuch operations. Therefore, conserving battery power can provide forlonger, uninterrupted operation of the implantable medical device. Manysystems utilize a sleep mode when a certain portion of a circuit in theimplantable medical device is not immediately needed, in order toconserve power. Often, a different clock rate may be used for a sleepmode operation, whereas a faster clock rate may be used for normaloperation that requires more robust circuit functions. For example,simple monitoring functions may be performed using a slower operationclock frequency while more complex circuitry in the implantable medicaldevice may be used in a sleep mode. Upon detection of a cardiac event, afast operation clock may be invoked in order to process acquiredphysiological data and deliver a cardiac therapy in response to theprocessing of the physiological data.

Often, when switching from one clock to another (e.g., switching from aslow clock to a fast clock), certain errors, ringing, false signalrises, etc., may occur. Such errors can cause malfunction of a circuitmaking the overall implantable medical system unreliable. Embodiments ofthe present invention provide for synchronizing clock signals during atransition from one clock-mode/domain to another.

FIG. 1 illustrates one embodiment of implementing an implantable medicaldevice into a human body. A sensor 210 (e.g., leads) placed upon theheart 116 of the human body 105 is used to acquire and processphysiological data. An implantable medical device 220 collects andprocesses a plurality of data acquired from the human body. In oneembodiment, the implantable medical device 220 may be a pacemaker or adefibrillator. The data acquired by the implantable medical device 220can be monitored by an external system, such as the access device 240comprising a programming head 122, which remotely communicates with theimplantable medical device 220. The programming head 122 is utilized inaccordance with medical device programming systems known those skilledin the art having the benefit of the present disclosure, forfacilitating two-way communications between the pacemaker 220 and theaccess device 240.

In one embodiment, a plurality of access devices 240 can be employed tocollect a plurality of data processed by the implantable medical device220 in accordance with embodiments of the present invention. Theimplantable medical device 220 is housed within a hermetically sealed,biologically inert outer canister or housing 113, which may itself beconductive so as to serve as an electrode in the pacemaker'spacing/sensing circuit. One or more pacemaker sensors/therapy-deliverydevices (leads), collectively identified with reference numeral 210 inFIG. 1 are electrically coupled to the pacemaker 220 and extend into thepatient's heart 116 via a vein 118. Disposed generally near a distal endof the sensors 210 are one or more exposed conductive electrodes forreceiving electrical cardiac signals or delivering electrical pacingstimuli to the heart 116. The sensors 210 may be implanted with theirdistal end situated in either the atrium or ventricle of the heart 116.In an alternative embodiment, the sensors 210, or the leads associatedwith the sensors 210, may be situated in a blood vessel on the heart116, such a save in 118.

Turning now to FIG. 2, a system 200, in accordance with one embodimentof the present invention, is illustrated. The system 200 comprises asensor 210, an implantable medical device 220, an access device 240, andan interface 230 that provides a communication link between theimplantable medical device 220 and the access device 240. Embodiments ofthe present invention provide a plurality of physiological data from thesensor 210, which are then processed and stored. The access device 240can then be used to monitor and analyze the organized data from theimplantable medical device via the interface 230.

Turning now to FIG. 3, a more detailed illustration of the access device240 is illustrated. In one embodiment, the access device 240 comprises acomputer system 310, a display device 320, and a programmer 330. In oneembodiment, the programmer 330 can be integrated into the computersystem 310. The computer system 310 can prompt the acquisition ofphysiological data from the implantable medical device 220 via theinterface 230. The computer system 310 can then display thephysiological data on the display device 320. The display device 320 candisplay physiological data from the reference point of different timeperiods, different activity results, and the like. Generally, theinterface 230 is a telemetry interface that is capable of facilitatingtwo-way communications between the access device 240 and the implantablemedical device 220. In one embodiment, the interface 230 provideswireless telemetry between the access device 240 and the implantablemedical device 220. A number of processes can be used for telemetrycommunications that are known by those skilled in the art having benefitof the present disclosure.

Turning now to FIG. 4, a more detailed block diagram depiction of oneembodiment of the implantable medical device 220 is illustrated. Theimplantable medical device 220 comprises a processor 410, a controllogic 420, a memory unit 430, a data acquisition controller 440, atelemetry interface 450, a slow clock generator 470, a fast clockgenerator 480, and a clock controller 490. The processor 410 controlsthe operation of the implantable medical device 220. The processor 410utilizes the control logic 420 to perform a plurality of operations,including memory access and storage operations, physiological dataprocessing, and therapy deliver operations. The processor 410communicates with the control logic 420 and the data acquisitioncontroller 440 via a bus line 425. The control logic 420 sends controlsignals to the memory unit 430 for controlling memory 430, and to thedata acquisition controller 440, which controls the acquisition ofphysiological data and drives output signals to the telemetry interface450.

The telemetry interface 450 can facilitate real-time access ofphysiological data acquired by the data acquisition controller 440.Therefore, a physician can view physiological data on a real time basisby accessing the data acquisition controller 440, via the telemetryinterface 450. The data acquisition controller 440 can retrievephysiological data, process such data, and deliver physiological data tothe data acquisition controller 440.

In one embodiment, the implantable medical device 220 invokes a slowclock generator 470 to enter a slow-clock mode (slow-clock domain),which utilizes less power. For example, the slow clock generator 470 mayproduce a clock of a frequency of approximately 32 kHz. The implantablemedical device 220 may invoke the operation of the fast clock generator480 to enter a fast-clock mode (fast-clock domain). For example, thefast clock generator 480 may generate a clock of a frequency ofapproximately 2.8 MHz. In one embodiment, the fast-clock mode is invokedwhen a physiological event (e.g., a cardiac event) is detected. In thefast-clock mode, all operations of the implantable medical device 220,such as physiological data processing and therapy delivery functions,are generally active. Furthermore, the fast-clock mode may be invoked atpredetermined intervals (e.g., once every 1000 milliseconds) to performdiagnostics operations, such as memory refreshing, lead diagnostics,battery measurements, and the like. In one embodiment, the transitionfrom a slow clock domain to a fast clock domain comprises changing thecircuit operation from a slow clock operating frequency to a fast clockoperating frequency during a non-transition period of the slow clock.

One reason for clock synchronization is that one or more signals maypass between the slow clock domain and the fast clock domain.Furthermore, in one embodiment, the use of the fast clock may be delayeduntil the slow clock is synchronized with the fast clock. Therefore, theinitial operation performed by the implatable medical device 220 in thefast clock mode would be in synchronized with the operation of thedevice 220 in the slow clock mode. The overall stability of thecircuitry in the implantable medical device 220 may be more stabilizedby employing the synchronization of clock domains.

The clock controller 490 in the implantable medical device 220 controlsat which frequency the circuitry in the implantable medical device 220operates. Generally, the fast clock generator 480 is used to operate theprocessor 410 and certain circuits, such as the memory unit 430, in theimplantable medical device 220. The slow clock generator 470 providesthe clock signal for the operation of certain circuitry in theimplantable medical device 220, such as the data acquisition controller440. During certain conditions, the slow clock generator 470 providesthe operational clock signals for the implantable medical device 220.Under circumstances such as a cardiac event or certain predetermineddiagnostic time frames, the fast clock generator 480 is invoked by theclock controller 490. The slow clock is used for certain operations toconserve power utilized by the implantable medical device 220.

Turning now to FIG. 5, a timing diagram illustrating a sample of eventsthat show the slow clock and the fast clock transitions, in accordancewith one embodiment of the present invention is illustrated. Asindicated in FIG. 5, approximately one-second intervals (1000millisecond), the fast clock generator 480 is invoked. This is done toperform certain circuit diagnostic functions. These diagnostic functionsinclude performing a memory refresh task, a logging of certain statussignals into memory, checking impedance and other electricalcharacteristics of the lead 210, common battery measurements, and thelike. In the interim, the operation of the implantable medical device220 is performed using the slow clock, from the slow clock generator470.

As shown in the example of FIG. 5, the implantable medical device 220operates at a slow clock frequency until the 1000 millisecond mark, thenthe fast clock is initiated. After performing certain diagnostics, thefast clock is stopped and the slow clock is operational. Subsequently,the fast clock generator is invoked again at the 2,000 millisecond mark,and the 3,000 millisecond mark, and so on. Upon detection of a cardiacevent by the implantable medical device 220, the fast clock isimmediately invoked, wherein the implantable medical device 220 is fullyoperational.

As illustrated in FIG. 5, after the 3,000 millisecond mark, theimplantable medical device 220 operates at a slow clock frequency untilthe cardiac event is detected. Once the response to the cardiac eventhas been performed, the implantable medical device 220 again invokes theslow clock for conservation of energy. Subsequently, at the 4,000 andthe 5,000 millisecond marks, the operation of the slow clock is replacedby the fast clock to perform diagnostics. The switching between the fastand the slow clocks can cause jitters, unintended rising edge in certaindigital signals, among other errors. Embodiments of the presentinvention reduce the possibility of the aforementioned errors during theswitching from the slow clock to the fast clock and vice versa.

Turning now to FIG. 6, a block diagram representation of an interactionbetween the fast clock generator 480, the slow clock generator 470, andthe clock controller 490 is illustrated. Clock frequency signalsgenerated by the fast clock generator 480 and the slow clock generator470 are sent to the clock controller 490. The clock controller 490controls the switching of certain digital signals that control the clockoperations of other circuitry in the implantable medical device 220. Theclock controller 490 provides a slow clock, and a slow sync clock, and afast clock. In an alternative embodiment, the slow sync clock and theslow clock are generally on one signal line. A more detailedrepresentation of the clock controller 490 is provided in FIG. 7.

Turning now to FIG. 7, the clock controller 490 comprises a D-flip-flop710, a multiplexer 720, and a state machine 730 that performs atransition from the slow clock operation to the fast clock operation.The slow clock generator 470 provides a slow clock signal (e.g., 32 KHzsignal) to the D-flip-flop 710 on a line 712. The D-flip-flop is alsoclocked by the fast clock generator 480 on a line 714. The D-flip-flop710 is then used to clock the slow clock signal from the line 712 ontothe output of the D-flip-flop 710 on the line 718.

The output of the D-flip-flop on the line 718 comprises a synced slowclock, which is synced (e.g., the rising and falling edge of the slowclock being synced to the rising edge of the fast clock) to the fastclock, therefore reducing any jitters or other errors on a transition.The synced slow clock is then sent to the A input 721 of a multiplexer720. The B input 722 to the multiplexer 720 is a signal directly fromthe slow clock generator 470, which is not synced. A select signal onthe line 716 is sent to the multiplexer 720 into its select input 723,from the state machine 740 for selection between the non-synced slowclock and the synced slow clock. Switching from the slow clock to thesynced slow clock is timed by the state machine 730 to coincide withinvoking the processor 410 in the implantable medical device 220.

Turning now to FIG. 8A, a timing diagram that shows the operation of theimplantable medical device 220 during a normal power-saving mode, isillustrated. During the normal power saving mode operation of theimplantable medical device 220 the slow clock is used for the operationand the fast clock line is a straight line (i.e., fast clock is notgenerated), indicating the fast clock does not exist at this time.During certain time frames described above, or upon detecting a cardiacevent, the implantable medical device 220 invokes the fast clock, wherethe processor and other peripheral devices are fully active in theimplantable medical device 220. As indicated in FIG. 8B, the timing ofthe synced clock is slightly different from the timing of the slowclock. However, the fast clock (e.g., the rising edge of the fast clock)is in sync with the rising and falling edge of the slow clock.Therefore, the probability of glitches and other errors during theinvocation of the fast clock is reduced.

The implantable medical device 220 may comprise components that operateat a plurality of frequencies that are multiples, or fractions, of thefast clock. Turning now to FIG. 9, a circuit for providing a syncedclock that has a fraction of the frequency of the fast clock, isillustrated. The fast clock is divided by a clock dividing circuit 910,which divides the fast clock by a value n. The value used to divide theclock dividing circuit is provided by the clock switching control unit920, which may comprise the state machine 730. The output of the clockdividing circuit is used to clock the slow clock through a flip-flop 930onto a multiplexer 940. Another input into the multiplexer 940 is slowclock. The clock switching control unit 920 selects between the slowclock and the synced, divided clock for operation of certain componentsin the implantable medical device 220. Therefore, a plurality of clocksignals that are synced can operate a plurality of components in theimplantable medical device 220.

Turning now to FIG. 10, a flowchart depiction of the method inaccordance with one embodiment of the present invention is illustrated.The system 200 determines a mode of operation for the operation of theimplantable medical device 220 (block 1010). In other words, the mode ofoperation may be a normal power save mode wherein certain componentssuch as a processor are in a low power mode, where the slow clock isused for the operation. Another mode may be one that is initiated by theoperation of the fast clock in which all components in the implantablemedical device 220 are invoked. Such a mode may be invoked by apredetermined diagnostic period, such as every 1,000 millisecond or bythe detection of a cardiac event in which a therapy response may berequired.

The implantable medical device 220 determines whether a normal mode isto be invoked (block 1020). When the implantable medical device 220determines that a normal mode is not invoked, the device 220 determineswhether there is a cardiac event (block 1030). When the device 220determines that there is no cardiac event, the device 220 again checksto determine which mode of operation is to be invoked. When theimplantable medical device 220 determines that a cardiac event hasoccurred (block 1030), the device 220 invokes the fast clock and theslow clock and fast clock domains are synchronized (block 1040). Untilthe cardiac event is terminated and/or all responses to the cardiacevent are completed, the fast clock is invoked such that all componentsin the implantable medical device 220 are operational at full capacity(see the loop from blocks 1050 to 1040 back to 1050). When the cardiacevent is over, the implantable medical device 220 places the operationof the device 220 into a slow clock mode (block 1060). At any givenpoint, when a cardiac event is detected, the implantable medical device220 is placed into a fast clock mode.

Referring to block 1020, when the device 220 determines that a normalmode is to be maintained, the slow clock is invoked (block 1070). Duringthe operation of the slow clock mode, the device 220 checks to determinewhether a predetermined diagnostic interval has occurred (block 1075).Furthermore, the device 220 checks to determine whether a cardiac eventhas occurred. When the implantable medical device 220 determines that apredetermined diagnostic time period has not occurred, the use of theslow clock is maintained. When the device 220 determines that a cardiacevent has occurred, clock domains are changed as described above (seepath from block 1075 to 1040). When the device 220 determines that apredetermined diagnostic time interval has been reached, the fast clockis invoked (block 1080). Subsequently, the device 220 syncs the fastclock to the slow clock (1085).

The implantable medical device 220 then determines whether thediagnostic process is complete as indicated by firmware in theimplantable medical device 220 (block 1090). When the diagnostic processis complete, the device 220 again goes back to the slow clock operation(the path from block 1090 to block 1060). When the implantable medicaldevice 220 determines that the diagnostic period is not over, theoperation of the fast clock is maintained. The end of the diagnosticprocess for the slow clock is once again maintained and is generallyprogrammed into firmware placed in the implantable medical device 220.

The operation described in FIG. 10, in one embodiment, can be performedby a state machine 730. One example of such a state machine 730, inaccordance with one embodiment of the present invention, is illustratedin FIG. 11. The initial state of the state machine 730 is an idle state(state 1110), until the insertion of the “signal oscillator highfrequency on” signal (osc_hf_on), which invokes the high frequencyclock. The operation of the high frequency clock is invoked in the state1120 and 1130, which are wait states. The wait state 0 has an input of areset signal, which brings the state machine 730 to state 1120. Thestate 1140 is a wait state until the edge of a slow clock signal (e.g.,32 kHz edge) is realized.

On the falling edge of the low frequency signal (e.g., 32 kHz signal),the assertion of an interrupt request, a wake up request, or a telemetryrequest is checked. If an interrupt request, a wake up request, or atelemetry request is detected, the state machine 730 jumps to the state1170. If no such request is detected, the slow clock is synced (state1160). The state 1160 is maintained until a shutdown request isreceived. The state machine 730 then moves to the state 1170, where await to shut down state is maintained. When an interrupt is received,the clock is synced (the state machine moves from state 1170 to 1160).When a telemetry and charge clock to charge the capacitor in the device220 are not active upon the falling edge of the 32 KHz signal, theshutting down state (state 1180) is reached, which then goes into theidle state 1110, awaiting the osc_hf_on signal. Alternative embodimentsof the implantation of the state machine 730 can be utilized and remainwithin the spirit of the present invention.

A timing diagram in relation to the state machine described in FIG. 11is provided in FIG. 12. The timing diagram illustrated in FIG. 12 tracksthe operation of the state machine 730, as described above. Furthermore,Appendix A provides one method of invoking the state machine 730 usinghardware descriptive language (HDL), as provided. Those skilled in theart, having the benefit of the present disclosure, can implement thestate machine 730 described above by referring to the hardwaredescriptive language (HDL) provided in Appendix A. The switching of theclock frequencies and the synchronizing of the clock domains describedby the present invention can be utilized in a variety of electricalcircuits including medical devices, commercial devices, computingdevices, and the like.

The above detailed description is an illustrative example of anembodiment in accordance with the present invention, of theimplementation of the implantable medical device 220 described above. Itshould be appreciated that other implementations and/or embodiments canbe employed within the spirit of the present invention. The teachings ofthe present invention can be utilized for a variety of systems relatingto data acquisition, data storage, or presentation of data.

The particular embodiments disclosed above are illustrative only, as theinvention may be modified and practiced in different but equivalentmanners apparent to those skilled in the art having the benefit of theteachings herein. Furthermore, no limitations are intended to thedetails of construction or design herein shown, other than as describedin the claims below. It is therefore evident that the particularembodiments disclosed above may be altered or modified and all suchvariations are considered within the scope and spirit of the invention.Accordingly, the protection sought herein is as set forth in the claimsbelow.

1. An implantable medical device, comprising: means to acquirephysiological data of a patient; means to deliver therapy to a patientbased upon acquired physiological data; a slow clock signal generatorproviding a slow clock signal; a fast clock signal generator providing afast clock signal; a clock controller coupled to said slow clock signalgenerator and to said fast clock signal generator, said clock controllerproviding a synchronized slow clock signal synchronized with a fastclock signal by latching a state of the slow clock signal upon eachoccurrence of a predetermined transition of the fast clock signal andproviding the fast clock signal; a processor controlling operations ofthe therapy delivery means; and a control logic circuit operativelycoupled to said processor and generating a control signal in response toa command from said processor to cause the clock controller toselectively apply the synchronized slow clock signal and the fast clocksignal to a clock driven circuit in the therapy delivery means.
 2. Theimplantable medical device of claim 1, wherein the processor sends acommand to the control logic circuit to apply the synchronized slowclock signal when patient circumstances permit a low power operation ofhe therapy delivery means.
 3. The implantable medical device of claim 2,wherein the processor sends a command to the control logic circuit toapply the fast clock signal when patient circumstances require a normaloperation of the therapy delivery means.
 4. The implantable medicaldevice of claim 1, wherein the processor executes a program ofinstructions to provide a power save mode of operation of the therapydelivery means and the processor that invokes use of the synchronizedslow clock signal and to provide a fully operational mode of operationof the therapy delivery means and the processor in response to a patientevent that invokes use of the fast clock signal.
 5. The implantablemedical device of claim 1, wherein the fast clock generator produces afast clock signal at a predetermined frequency and the clock controllerincludes a clock dividing circuit coupled to the fast clock generator toprovide a clock signal that is a fraction of the frequency of the fastclock signal.
 6. The implantable medical device of claim 1, wherein themeans to acquire physiological data of a patient, the means to delivertherapy to a patient based upon acquired physiological data, and theprocessor implement a cardiac pacemaker.
 7. The implantable medicaldevice of claim 6, wherein the processor executes a program ofinstructions to provide a power save mode of operation of the therapydelivery means and the processor that invokes use of the synchronizedslow clock signal and to provide a fully operational mode of operationof the therapy delivery means and the processor in response to a patientcardiac event that invokes use of the fast clock signal.